A. Technical Field
The present invention relates to test pattern generation and, more particularly, to the generation of user-defined test patterns for signal characterization and testing.
B. Background of the Invention
The application and importance of test pattern generators is well known. Pattern generators provide a test signal used for signal characterization and analysis within various electrical components and systems. These test patterns are used for testing devices such as integrated chips, systems, and communication paths to ensure proper operation of these devices and systems.
The current solution for pattern generation allows a user to select one or more pre-stored “canned data patterns” within the memory of a testing device or device-under-test. Typically, the canned patterns are generated by looping a small pattern over multiple times in sequence to generate a longer test pattern. For example, the SAS/Fibre Channel specification defines a test pattern called “JPAT” that is composed of five smaller pieces or patterns. These five smaller patterns are effectively repeated a number of times to build a larger pattern that is compliant with the specification.
During a test procedure using the pattern, a state machine may be adapted to count the number of repeats and to transmit a previous part to the next part of the pattern; thereby creating the full pattern in real time. This is generally used in conjunction with a pattern checker for comparing the data coming into the device under test and logging errors.
It is important that a test engineer be able to test the boundaries of a system so that as many potential errors may be identified prior to the device or system being activated. If an envelope of performance is to be tested, a system level test will eventually fail and require a long startup time to get back to a working point. In order to determine these limits, an engineer needs to be able to toggle around the potential failing points and tune the test equipment to zoom in on the actual parameters that cause the failure.
FIG. 1 depicts an exemplary prior art operation of generating a test pattern in a chip 101 and analyzing the same in an external analysis device 105. This existing solution uses stored or “canned” patterns within a memory 103 to generate the test pattern. The stored patterns may be a small pattern or sequence that may be repeatedly used by a pattern generator 102 to generate the large test patterns. The stored patterns in the memory 103 may be selected by a user and transmitted one-by-one over a high-speed serial interface 104 such as a PCI express bus, USB or other type of interface known to one of skill in the art.
The canned test pattern may be generated in a burst by propagating the pattern bits one at a time using the serial interface. Building these large sequences is important to comply with various rules and regulations of certain standard protocols. The canned pattern bits may be transmitted to an external analysis device 105, such as an oscilloscope for analysis. However, the sequence of data within the large test pattern is specifically limited by the canned patterns stored within the memory 103.
These pattern generators cannot be dynamically configured since they are confined to the pre-stored sequences thereof. Accordingly, what is desired are a system, apparatus and method that provides more dynamic generation of test patterns.